1. Field of the disclosure
The present innovation relates to efficient design and implementation of artificial neural networks.
2. Description of Related Art
Most existing neuronal models and systems include networks of simple units, called neurons, which interact with each other via connections called synapses. The information processing in such neuronal systems may be carried out in parallel.
There are many specialized software tools that may help neuroscientists simulate models of neural systems. Examples of these tools may include high-level implementations such as one or more of NEURON, GENESIS, NEST, BRIAN, and/or other high-level implementations may be designed primarily for use by neuroscientists. Such tools may typically require substantial specialized knowledge, may be cumbersome, and may require customization in order to achieve efficient performance during simulations that are executed using specific software and hardware engines, particularly when real-time performance is required, as in autonomous robotics applications.
Similarly, low-level implementations such as one or more of assembly languages, low-level virtual machine (LLVM) language, Java Bytecode, chip-specific instruction sets, and/or other low-level implementations may be designed for efficient hardware implementations on x86, ARM™, and/or other silicon chips. However, such implementations may be unsuitable for parallel simulations of neuronal systems, mostly because the silicon chips are not designed for such parallel neuronal simulations.
Overall, existing approaches have substantial shortcomings as they do not provide sufficient flexibility in designing neural networks, require expert knowledge, and/or platform specific customization in order to take advantage of specialized hardware.
Accordingly, there is a salient need for a universal high level network description for defining network architectures in a simple and unambiguous way that is both human-readable and machine-interpretable.